426 lines
14 KiB
C
426 lines
14 KiB
C
/*
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* Register definitions for STM8S103 (and STM8S003)
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* Still incomplete.
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*/
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#ifndef _STH8_H
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#define _STH8_H
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/* Handy macros for GPIO */
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#define CONCAT(a, b) a##_##b
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#define PORT(a, b) CONCAT(a, b)
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#define PIN0 (1 << 0)
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#define PIN1 (1 << 1)
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#define PIN2 (1 << 2)
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#define PIN3 (1 << 3)
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#define PIN4 (1 << 4)
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#define PIN5 (1 << 5)
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#define PIN6 (1 << 6)
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#define PIN7 (1 << 7)
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/* Register addresses */
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/* Clock */
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#define CLK_CKDIVR *(volatile unsigned char *)0x50C6
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/* GPIO */
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#define PA_ODR *(volatile unsigned char *)0x5000
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#define PA_IDR *(volatile unsigned char *)0x5001
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#define PA_DDR *(volatile unsigned char *)0x5002
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#define PA_CR1 *(volatile unsigned char *)0x5003
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#define PA_CR2 *(volatile unsigned char *)0x5004
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#define PB_ODR *(volatile unsigned char *)0x5005
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#define PB_IDR *(volatile unsigned char *)0x5006
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#define PB_DDR *(volatile unsigned char *)0x5007
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#define PB_CR1 *(volatile unsigned char *)0x5008
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#define PB_CR2 *(volatile unsigned char *)0x5009
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#define PC_ODR *(volatile unsigned char *)0x500A
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#define PC_IDR *(volatile unsigned char *)0x500B
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#define PC_DDR *(volatile unsigned char *)0x500C
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#define PC_CR1 *(volatile unsigned char *)0x500D
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#define PC_CR2 *(volatile unsigned char *)0x500E
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#define PD_ODR *(volatile unsigned char *)0x500F
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#define PD_IDR *(volatile unsigned char *)0x5010
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#define PD_DDR *(volatile unsigned char *)0x5011
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#define PD_CR1 *(volatile unsigned char *)0x5012
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#define PD_CR2 *(volatile unsigned char *)0x5013
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#define EXTI_CR1 *(volatile unsigned char *)0x50A0
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#define EXTI_CR2 *(volatile unsigned char *)0x50A1
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/* UART */
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#define UART1_SR *(volatile unsigned char *)0x5230
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#define UART1_DR *(volatile unsigned char *)0x5231
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#define UART1_BRR1 *(volatile unsigned char *)0x5232
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#define UART1_BRR2 *(volatile unsigned char *)0x5233
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#define UART1_CR1 *(volatile unsigned char *)0x5234
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#define UART1_CR2 *(volatile unsigned char *)0x5235
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#define UART1_CR3 *(volatile unsigned char *)0x5236
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#define UART1_CR4 *(volatile unsigned char *)0x5237
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#define UART1_CR5 *(volatile unsigned char *)0x5238
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#define UART1_GTR *(volatile unsigned char *)0x5239
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#define UART1_PSCR *(volatile unsigned char *)0x523A
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#define UART_SR_TXE (1 << 7)
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#define UART_SR_TC (1 << 6)
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#define UART_SR_RXNE (1 << 5)
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#define UART_SR_IDLE (1 << 4)
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#define UART_SR_OR (1 << 3)
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#define UART_SR_NF (1 << 2)
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#define UART_SR_FE (1 << 1)
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#define UART_SR_PE (1 << 0)
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#define UART_CR1_R8 (1 << 7)
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#define UART_CR1_T8 (1 << 6)
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#define UART_CR1_UARTD (1 << 5)
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#define UART_CR1_M (1 << 4)
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#define UART_CR1_WAKE (1 << 3)
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#define UART_CR1_PCEN (1 << 2)
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#define UART_CR1_PS (1 << 1)
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#define UART_CR1_PIEN (1 << 0)
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#define UART_CR2_TIEN (1 << 7)
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#define UART_CR2_TCIEN (1 << 6)
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#define UART_CR2_RIEN (1 << 5)
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#define UART_CR2_ILIEN (1 << 4)
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#define UART_CR2_TEN (1 << 3)
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#define UART_CR2_REN (1 << 2)
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#define UART_CR2_RWU (1 << 1)
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#define UART_CR2_SBK (1 << 0)
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#define UART_CR3_LINEN (1 << 6)
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#define UART_CR3_STOP2 (1 << 5)
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#define UART_CR3_STOP1 (1 << 4)
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#define UART_CR3_CLKEN (1 << 3)
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#define UART_CR3_CPOL (1 << 2)
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#define UART_CR3_CPHA (1 << 1)
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#define UART_CR3_LBCL (1 << 0)
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/* Timers */
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#define TIM1_CR1 *(volatile unsigned char *)0x5250
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#define TIM1_CR2 *(volatile unsigned char *)0x5251
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#define TIM1_SMCR *(volatile unsigned char *)0x5252
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#define TIM1_ETR *(volatile unsigned char *)0x5253
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#define TIM1_IER *(volatile unsigned char *)0x5254
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#define TIM1_SR1 *(volatile unsigned char *)0x5255
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#define TIM1_SR2 *(volatile unsigned char *)0x5256
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#define TIM1_EGR *(volatile unsigned char *)0x5257
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#define TIM1_CCMR1 *(volatile unsigned char *)0x5258
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#define TIM1_CCMR2 *(volatile unsigned char *)0x5259
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#define TIM1_CCMR3 *(volatile unsigned char *)0x525A
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#define TIM1_CCMR4 *(volatile unsigned char *)0x525B
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#define TIM1_CCER1 *(volatile unsigned char *)0x525C
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#define TIM1_CCER2 *(volatile unsigned char *)0x525D
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#define TIM1_CNTRH *(volatile unsigned char *)0x525E
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#define TIM1_CNTRL *(volatile unsigned char *)0x525F
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#define TIM1_PSCRH *(volatile unsigned char *)0x5260
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#define TIM1_PSCRL *(volatile unsigned char *)0x5261
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#define TIM1_ARRH *(volatile unsigned char *)0x5262
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#define TIM1_ARRL *(volatile unsigned char *)0x5263
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#define TIM1_RCR *(volatile unsigned char *)0x5264
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#define TIM1_CCR1H *(volatile unsigned char *)0x5265
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#define TIM1_CCR1L *(volatile unsigned char *)0x5266
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#define TIM1_CCR2H *(volatile unsigned char *)0x5267
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#define TIM1_CCR2L *(volatile unsigned char *)0x5268
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#define TIM1_CCR3H *(volatile unsigned char *)0x5269
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#define TIM1_CCR3L *(volatile unsigned char *)0x526A
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#define TIM1_CCR4H *(volatile unsigned char *)0x526B
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#define TIM1_CCR4L *(volatile unsigned char *)0x526C
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#define TIM1_BKR *(volatile unsigned char *)0x526D
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#define TIM1_DTR *(volatile unsigned char *)0x526E
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#define TIM1_OISR *(volatile unsigned char *)0x526F
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/* Note these are for STM8S103 and STM8S003
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STM8S105,104/207/208 are different */
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#define TIM2_CR1 *(volatile unsigned char *)0x5300
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#define TIM2_CR2 *(volatile unsigned char *)0x5301
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#define TIM2_SMCR *(volatile unsigned char *)0x5302
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#define TIM2_IER *(volatile unsigned char *)0x5303
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#define TIM2_SR1 *(volatile unsigned char *)0x5304
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#define TIM2_SR2 *(volatile unsigned char *)0x5305
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#define TIM2_EGR *(volatile unsigned char *)0x5306
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#define TIM2_CCMR1 *(volatile unsigned char *)0x5307
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#define TIM2_CCMR2 *(volatile unsigned char *)0x5308
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#define TIM2_CCMR3 *(volatile unsigned char *)0x5309
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#define TIM2_CCER1 *(volatile unsigned char *)0x530A
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#define TIM2_CCER2 *(volatile unsigned char *)0x530B
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#define TIM2_CNTRH *(volatile unsigned char *)0x530C
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#define TIM2_CNTRL *(volatile unsigned char *)0x530D
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#define TIM2_PSCR *(volatile unsigned char *)0x530E
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#define TIM2_ARRH *(volatile unsigned char *)0x530F
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#define TIM2_ARRL *(volatile unsigned char *)0x5310
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#define TIM2_CCR1H *(volatile unsigned char *)0x5311
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#define TIM2_CCR1L *(volatile unsigned char *)0x5312
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#define TIM2_CCR2H *(volatile unsigned char *)0x5313
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#define TIM2_CCR2L *(volatile unsigned char *)0x5314
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#define TIM2_CCR3H *(volatile unsigned char *)0x5315
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#define TIM2_CCR3L *(volatile unsigned char *)0x5316
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#define TIM2_CR1_CEN (1 << 0)
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#define TIM2_CCER1_CC1P (1 << 1)
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#define TIM2_CCER1_CC1E (1 << 0)
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#define TIM2_CCER1_CC2P (1 << 5)
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#define TIM2_CCER1_CC2E (1 << 4)
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#define TIM2_CCER2_CC3P (1 << 1)
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#define TIM2_CCER2_CC3E (1 << 0)
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#define TIM2_CCMR2_OC2M0 (1 << 4)
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#define TIM2_CCMR2_OC2M1 (1 << 5)
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#define TIM2_CCMR2_OC2M2 (1 << 6)
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/* Note these are for STM8S103 and STM8S003
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STM8S105,104/207/208 are different */
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#define TIM4_CR1 *(volatile unsigned char *)0x5340
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#define TIM4_CR2 *(volatile unsigned char *)0x5341
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#define TIM4_SMCR *(volatile unsigned char *)0x5342
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#define TIM4_IER *(volatile unsigned char *)0x5343
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#define TIM4_SR *(volatile unsigned char *)0x5344
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#define TIM4_EGR *(volatile unsigned char *)0x5345
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#define TIM4_CNTR *(volatile unsigned char *)0x5346
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#define TIM4_PSCR *(volatile unsigned char *)0x5347
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#define TIM4_ARR *(volatile unsigned char *)0x5348
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#define TIM_IER_BIE (1 << 7)
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#define TIM_IER_TIE (1 << 6)
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#define TIM_IER_COMIE (1 << 5)
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#define TIM_IER_CC4IE (1 << 4)
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#define TIM_IER_CC3IE (1 << 3)
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#define TIM_IER_CC2IE (1 << 2)
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#define TIM_IER_CC1IE (1 << 1)
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#define TIM_IER_UIE (1 << 0)
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#define TIM_CR1_APRE (1 << 7)
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#define TIM_CR1_CMSH (1 << 6)
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#define TIM_CR1_CMSL (1 << 5)
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#define TIM_CR1_DIR (1 << 4)
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#define TIM_CR1_OPM (1 << 3)
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#define TIM_CR1_URS (1 << 2)
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#define TIM_CR1_UDIS (1 << 1)
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#define TIM_CR1_CEN (1 << 0)
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#define TIM_SR1_BIF (1 << 7)
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#define TIM_SR1_TIF (1 << 6)
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#define TIM_SR1_COMIF (1 << 5)
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#define TIM_SR1_CC4IF (1 << 4)
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#define TIM_SR1_CC3IF (1 << 3)
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#define TIM_SR1_CC2IF (1 << 2)
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#define TIM_SR1_CC1IF (1 << 1)
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#define TIM_SR1_UIF (1 << 0)
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/* SPI */
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#define SPI_CR1 *(volatile unsigned char *)0x5200
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#define SPI_CR2 *(volatile unsigned char *)0x5201
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#define SPI_ICR *(volatile unsigned char *)0x5202
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#define SPI_SR *(volatile unsigned char *)0x5203
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#define SPI_DR *(volatile unsigned char *)0x5204
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#define SPI_CRCPR *(volatile unsigned char *)0x5205
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#define SPI_RXCRCR *(volatile unsigned char *)0x5206
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#define SPI_TXCRCR *(volatile unsigned char *)0x5207
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#define SPI_CR1_LSBFIRST (1 << 7)
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#define SPI_CR1_SPE (1 << 6)
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#define SPI_CR1_BR(br) ((br) << 3)
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#define SPI_CR1_MSTR (1 << 2)
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#define SPI_CR1_CPOL (1 << 1)
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#define SPI_CR1_CPHA (1 << 0)
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#define SPI_CR2_BDM (1 << 7)
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#define SPI_CR2_BDOE (1 << 6)
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#define SPI_CR2_CRCEN (1 << 5)
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#define SPI_CR2_CRCNEXT (1 << 4)
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#define SPI_CR2_RXONLY (1 << 2)
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#define SPI_CR2_SSM (1 << 1)
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#define SPI_CR2_SSI (1 << 0)
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#define SPI_ICR_TXIE (1 << 7)
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#define SPI_ICR_RXIE (1 << 6)
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#define SPI_ICR_ERRIE (1 << 5)
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#define SPI_ICR_WKIE (1 << 4)
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#define SPI_SR_BSY (1 << 7)
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#define SPI_SR_OVR (1 << 6)
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#define SPI_SR_MODF (1 << 5)
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#define SPI_SR_CRCERR (1 << 4)
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#define SPI_SR_WKUP (1 << 3)
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#define SPI_SR_TXE (1 << 1)
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#define SPI_SR_RxNE (1 << 0)
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/* I2C */
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#define I2C_CR1 *(volatile unsigned char *)0x5210
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#define I2C_CR2 *(volatile unsigned char *)0x5211
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#define I2C_FREQR *(volatile unsigned char *)0x5212
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#define I2C_OARL *(volatile unsigned char *)0x5213
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#define I2C_OARH *(volatile unsigned char *)0x5214
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#define I2C_DR *(volatile unsigned char *)0x5216
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#define I2C_SR1 *(volatile unsigned char *)0x5217
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#define I2C_SR2 *(volatile unsigned char *)0x5218
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#define I2C_SR3 *(volatile unsigned char *)0x5219
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#define I2C_ITR *(volatile unsigned char *)0x521A
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#define I2C_CCRL *(volatile unsigned char *)0x521B
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#define I2C_CCRH *(volatile unsigned char *)0x521C
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#define I2C_TRISER *(volatile unsigned char *)0x521D
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#define I2C_PECR *(volatile unsigned char *)0x521E
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/* ADC */
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#define ADC_DBxR *(volatile unsigned char *)0x53E0
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#define ADC_CSR *(volatile unsigned char *)0x5400
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#define ADC_CR1 *(volatile unsigned char *)0x5401
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#define ADC_CR2 *(volatile unsigned char *)0x5402
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#define ADC_CR3 *(volatile unsigned char *)0x5403
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#define ADC_DRH *(volatile unsigned char *)0x5404
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#define ADC_DRL *(volatile unsigned char *)0x5405
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#define ADC_TDRH *(volatile unsigned char *)0x5406
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#define ADC_TDRL *(volatile unsigned char *)0x5407
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#define ADC_HTRH *(volatile unsigned char *)0x5408
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#define ADC_HTRL *(volatile unsigned char *)0x5409
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#define ADC_LTRH *(volatile unsigned char *)0x540A
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#define ADC_LTRL *(volatile unsigned char *)0x540B
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#define ADC_AWSRH *(volatile unsigned char *)0x540C
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#define ADC_AWSRL *(volatile unsigned char *)0x540D
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#define ADC_AWCRH *(volatile unsigned char *)0x540E
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#define ADC_AWCRL *(volatile unsigned char *)0x540F
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#define ADC_CSR_EOC (1 << 7)
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#define ADC_CSR_AWD (1 << 6)
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#define ADC_CSR_EOCIE (1 << 5)
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#define ADC_CSR_AWDIE (1 << 4)
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#define ADC_CR1_CONT (1 << 1)
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#define ADC_CR1_ADON (1 << 0)
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#define ADC_CR2_EXTTRIG (1 << 6)
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#define ADC_CR2_EXTSEL (1 << 4)
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#define ADC_CR2_ALIGN (1 << 3)
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#define ADC_CR2_SCAN (1 << 1)
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/* BEEP */
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#define BEEP_CSR *(volatile unsigned char *)0x50F3
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#define BEEP_CSR_EN (1 << 5)
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#define BEEP_CSR_SEL(sel) ((sel & 0b00000011) << 6)
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#define BEEP_CSR_DIV(div) ((div & 0b00011111) << 0)
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#define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */
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#define BEEP_FREQUENCY_1KHZ ((uint8_t)0x00) /*!< Beep signal output frequency equals to 1 KHz */
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#define BEEP_FREQUENCY_2KHZ ((uint8_t)0x40) /*!< Beep signal output frequency equals to 2 KHz */
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#define BEEP_FREQUENCY_4KHZ ((uint8_t)0x80) /*!< Beep signal output frequency equals to 4 KHz */
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#define BEEP_CALIBRATION_DEFAULT ((uint8_t)0x0B) /*!< Default value when calibration is not done */
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#define LSI_FREQUENCY_MIN ((uint32_t)110000) /*!< LSI minimum value in Hertz */
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#define LSI_FREQUENCY_MAX ((uint32_t)150000) /*!< LSI maximum value in Hertz */
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/* FLASH */
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#define FLASH_IAPSR *(volatile unsigned char *)0x505F
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#define FLASH_IAPSR_DUL (1 << 3)
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#define FLASH_IAPSR_EOP (1 << 2)
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#define FLASH_PUKR_KEY1 0x56
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#define FLASH_PUKR_KEY2 0xAE
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#define FLASH_DUKR *(volatile unsigned char *)0x5064
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#define FLASH_DUKR_KEY1 FLASH_PUKR_KEY2
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#define FLASH_DUKR_KEY2 FLASH_PUKR_KEY1
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#define EEPROM_START_ADDR 0x4000
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#define EEPROM_END_ADDR 0x407F
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/* Interrupt commands */
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#define enableInterrupts() \
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{ \
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__asm__("rim\n"); \
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} /* enable interrupts */
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#define disableInterrupts() \
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{ \
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__asm__("sim\n"); \
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} /* disable interrupts */
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#define rim() \
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{ \
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__asm__("rim\n"); \
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} /* enable interrupts */
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#define sim() \
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{ \
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__asm__("sim\n"); \
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} /* disable interrupts */
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#define nop() \
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{ \
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__asm__("nop\n"); \
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} /* No Operation */
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#define trap() \
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{ \
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__asm__("trap\n"); \
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} /* Trap (soft IT) */
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#define wfi() \
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{ \
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__asm__("wfi\n"); \
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} /* Wait For Interrupt */
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#define halt() \
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{ \
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__asm__("halt\n"); \
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} /* Halt */
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/* Interrupt numbers */
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#define TIM1_OVR_UIF_IRQ 11
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#define TIM2_OVR_UIF_IRQ 13
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#define TIM3_OVR_UIF_IRQ 15
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#define ADC1_EOC_IRQ 22
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#define TIM4_OVR_UIF_IRQ 23
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#define ISR(name, vector) void name(void) __interrupt(vector - 2)
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#define EXTI_PORTA_vector 0x05
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#define EXTI_PORTB_vector 0x06
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/*
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Interrupts:
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0 TLI
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1 AWU Auto Wake up from Halt
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2 CLK Clock controller
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3 EXTI0 Port A external interrupts
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4 EXTI1 Port B external interrupts
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5 EXTI2 Port C external interrupts
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6 EXTI3 Port D external interrupts
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7 EXTI4 Port E external interrupts
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8 CAN CAN RX interrupt
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9 CAN CAN TX/ER/SC interrupt
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10 SPI End of Transfer
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11 TIM1 Update /Overflow/Underflow/Trigger/Break
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12 TIM1 Capture/Compare
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13 TIM2 Update /Overflow
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14 TIM2 Capture/Compare
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15 TIM3 Update /Overflow
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16 TIM3 Capture/Compare
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17 UART1 Tx complete
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18 UART1 Receive Register DATA FULL
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19 I2C I2C interrupt
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20 UART2/3 Tx complete
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21 UART2/3 Receive Register DATA FULL
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22 ADC End of Conversion
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23 TIM4 Update/Overflow
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24 FLASH EOP/WR_PG_DIS
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TLI 0
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AWU 1
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CLK 2
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EXTI_PORTA 3
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EXTI_PORTB 4
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EXTI_PORTC
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EXTI_PORTD
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EXTI_PORTE
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CAN_RX
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CAN_TX
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SPI
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TIM1_UPD_OVF_TRG_BRK
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TIM1_CAP_COM
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TIM2_UPD_OVF_BRK
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TIM2_CAP_COM
|
|
TIM3_UPD_OVF_BRK
|
|
TIM3_CAP_COM
|
|
UART1_TX
|
|
UART1_RX
|
|
I2C 19
|
|
ADC1 22
|
|
TIM4_UPD_OVF 23
|
|
EEPROM_EEC 24
|
|
*/
|
|
|
|
#endif
|